Photonic detector devices respond to received photons by creating an electric effect which can be quantified and hence provide information as regards the flux of the received photons. Focal plane arrays (FPAs) of detectors are used to obtain images of objects, whereby each detector provides a pixel in is the image array. In the image, each pixel is provided with a unique address and a numeric value, which can further be used for manipulating the image for extracting information from the image.
Thermal Infra red (IR) FPAs are used for obtaining images in the thermal IR range. The resolution of an imaging array in the IR is limited by two factors, namely noise equivalent temperature (NET) and spatial noise, of the analog chain: the focal plane processor (FPP), the external analog circuitry and the analog to digital conversion. An external interference, such as RF interference or signals induced by the digital system may also degrade the performance. The temporal noise of the FPP can be reduced by careful design to be negligible relative to the signal noise, providing low NET values. Yet, to overcome the spatial noise, an external process of non uniformity correction (NUC) must be carried out. A “two point correction” process is generally used, assuming the analog chain to be linear and having stable offset and gain. The final results depend upon the validity of these assumptions, and the spatial resolution becomes a main restriction, limiting the dynamic range and requiring frequent calibrations. The FPP is kept at a steady temperature, e.g. at about 77° K while the external circuitry is exposed to wide temperature variations, degrading the gain and offset stability. Also, the FPP is relatively shielded against external interference, which is not the case with the external elements. In order to reach such a low temperature and keep it steady, the sensor is disposed within a cooled dewar. The dewar has electric connections installed in the walls, in order to facilitate electrical connection with external circuits.
Heat production is a matter of high importance in the design of FPPs. The efficiency of the cooling system being very low, the amount of power consumed by the circuits of the FPP at any time must also be limited. Sampling rates, sampling resolution, and output rates are factors which affect heat production. The use of components and combinations thereof having a low power consumption is favoured in the design of cooled FPPs. A trade-off between imaging parameters is a compromise often imposed for obtaining desirable image parameters. Accordingly, image frame rate at the expense of image resolution or image size are known in the art. Continuous attempts are made by various system designers to overcome the limitations described, striving to attain a high frame rate and a high resolution, with a reasonable power dissipation.
The value of the electric effect associated with each detector of the FPA is converted into a digital format, before it can be subjected to digital image processing. However, there are a number of critical reasons favouring conversion to digital format at an early stage as possible of the signal corresponding to each pixel. U.S. Pat. No. 5,886,659 discloses an on-focal plane analog to digital conversion application. Benefits of having the analog-to-digital conversion in the focal plane are discussed in that publication, the contents of which are incorporated herewith by reference.
Integrated converters have used several types of conversion schemes. Single-slope analog to digital conversion is a well-established technique. For example, U.S. Pat. No. 5,742,058 discloses an analog to digital conversion in the focal plane utilizing a single slope conversion cycle. The Dual-slope conversion provides better accuracy and stability (R. Van De Plassche, cited below). Yet, both techniques require quite long conversion times, being based on counters: the full-scale time of an n-bit single-slope converter is 2n*Tc, where Tc is the clock cycle time. The dual slope requires up to twice that time. The dual-ramp single-slope method, described by R. Van De Plassche in: INTEGRATED ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS, Kluwer Academic Press, pp. 274–289, 1994, the contents of which are incorporated herein by reference, promises both high resolution and reduced conversion time.
It is on the background hitherto described, that the present invention was conceived. The invention described below provides a basis for increasing the rate of sampling digitally at the FPP level, without compromising the resolution of each pixel.